SR Latch Explained: Set, Reset, Gated, and Clocked Versions

An SR latch is one of the simplest memory circuits. It stores just one bit, either a 1 or a 0. The name comes from its two inputs: Set (S) and Reset (R).

If you tell it to Set, the output goes high and stays there. If you tell it to Reset, the output goes low and stays there. If you do nothing, it just keeps whatever it already had. That’s all it does, a one-bit memory.

Basic SR Latch

Inputs:

• S for Set
• R for Reset

Output:

• Q (sometimes also Q̅, which is just the opposite)

Behavior:

• S=1, R=0 → Q becomes 1
• S=0, R=1 → Q becomes 0
• S=0, R=0 → Q stays the same as before
• S=1, R=1 → not allowed, it gets unstable

That’s the whole idea. Simple but powerful.

Gated SR Latch

Now imagine the same circuit, but you add an extra input called Enable.

• Enable = 1 → latch works normally with Set and Reset.
• Enable = 0 → latch ignores Set and Reset, output just stays where it is.

So the Enable is like a switch that decides if the latch should listen to changes or not.

Clocked SR Latch

Take the Gated version and swap Enable for a Clock input.

Now the latch doesn’t respond all the time. It only updates when the clock ticks, usually on the rising or falling edge of the signal.

So:

• Set → Q=1 (but only on the clock edge)
• Reset → Q=0 (but only on the clock edge)
• No inputs → stays the same
• Both high → invalid, same problem as before

This edge-triggered version is basically what people call the SR Flip-Flop.

Summary

• SR Latch → remembers 1 bit, controlled by S and R.
• Gated SR Latch → same thing, but with an Enable line.
• Clocked SR Latch (SR Flip-Flop) → same rules, but controlled by a clock edge.

These are the basic building blocks for memory, registers, and sequential logic.

This writing references: SR Latch Tutorial