Introduction
With the rapid development of the current mobile storage technology and the rapid expansion of the mobile storage market, the amount of FLASH memory is growing rapidly. FLASH chips are very suitable for mobile products due to their advantages of portability, reliability and low cost. The market demand has spawned a large number of FLASH chip research and development, production and application companies. In order to ensure the long-term reliable operation of the chip, these companies need to test the FLASH memory at high speed and meticulously before the product to the market. Therefore, it is very necessary to have the high-efficiency FLASH memory test.
1 FLASH Memory Test
No matter what type of electronic memory is tested, it is not easy. It cannot be concluded by testing each storage unit in the memory in turn, because the change of each storage unit may affect other units in the memory. This correlation creates a huge testing work. In addition, FLASH memory has its own characteristics. It can only write the data in the storage unit from “1” to “0”, but not from “0” to “1”. If you want to achieve “0” -> ” 1″ , only the data of the entire sector or the entire memory can be erased, and which takes a lot of time. FLASH memory has other characteristics, such as slow read and write speed, write status word before writing data, many FLASH are only suitable for sequential read and write but not suitable for jump operations, etc. Here these characteristics restrict the test of FLASH memory.
In order to solve these problems in FLASH testing, people have proposed using built-in self-testing or using embedded software and other testing methods to test related performance, which have achieved good results, but most of these methods are not suitable for product testing. However, most of the algorithms that are very effective for general-purpose memory testing are difficult to directly apply to FLASH testing due to the limitations of the FLASH device itself (for example, it cannot be directly written from “0” to “1”).
After a brief introduction to the structure and characteristics of the FLASH chip, the principle of the FLASH memory test program is explained. On this basis, several common memory testing methods are analyzed and improved, so that they can be effectively used in FLASH testing. These methods are simple and efficient, have high fault incidence, and can be quickly pre-generated. Compared with some other test algorithms, they are more suitable for engineering testing in testers. This paper analyzes the main characteristics of these methods, and on this basis, introduces the flow applied in the actual FLASH memory test.
2 FLASH Structural Features
There are various types of FLASH memories, and the most commonly used ones are NOR type and NAND type FLASH. Usually, the NOR type is more suitable for storing program codes. Its random read and write speed is fast, but the capacity is generally small (for example, less than 32 MB), and the price is high; while the NAND-type has a capacity of more than 1GB, and the price is relatively cheap, suitable for storage, but generally can only read and write data in a whole block, and the RAM capability is poor. They do not use linear address mapping to access data, but serially take register operations.
FLASH Chip Erase Flow
Generally speaking, no matter what type of FLASH, there is an ID register to read the memory information, and the specific type can be judged according to the chip data provided by the supplier. In addition, the erasing process of the FLASH memory is relatively time-consuming, and the erasing process is relatively complicated. Figure shows the general flow of FLASH chip erasing.
It can be seen that the operation of erasing data limits the working speed of the FLASH chip. In addition, some other features, such as slow reading and writing speed, writing the status word before writing data, many FLASHs are equipped with redundant units, etc., which restrict the improvement of the test speed. Therefore, it is very necessary to design a reasonable method, or to test several pieces of FLASH together, and to apply the test algorithm to reduce the test time.
3 FLASH Test Method
3.1 System Connection
The chips selected in this article are AMD's NOR type FLASH – AM29LV400B and Samsung's NAND type FLASH K9F5608UOB, which can be directly connected to the digital channel of the digital circuit tester through a 44 PIN special adapter. The hardware experiment platform we use is the BC3192 digital-analog hybrid test system. This system can provide fast working speed and flexible algorithm graphics generation method, which is very suitable for testing needs.
3.2 Test Implementation Method
Assuming that the number of memory cells that can be addressed by the memory is N, since the memory chip can only access one memory cell at a time, and each cell has only two states of “0” or “1”, there are 2N possible states in total. Since the selected addresses are random, when the number of test steps is M, there may be as many combinations of address selection sequences, even with all “0” or all “1” pattern testing, which is a huge number.
In order to effectively test the memory chip, the structure of the semiconductor memory must be analyzed, and several patterns that can effectively test the memory function must be determined and selected, so as to achieve the detection purpose and limit the test amount within the allowable range. However, in practical applications, because each test pattern has its limitations, and the characteristics of various manufacturers and various types of memories are not completely consistent, there is no optimal unified test method yet.
According to the characteristics of FLASH chips, we mainly improve and use the following methods:
1) Parity Pattern Check
Parity pattern check method is a more suitable method for memory testing. In the parity pattern check method, the data pattern written to the memory cell matrix is determined according to the parity of the memory cell address code. If there are an even number of 1s in the row address code and column address code of a memory cell, and its parity is 0, write “0” (or “1”) in the memory cell; if there are an odd number of 1s, its parity is 0, or it is 1, then write “1” (or “0”) in the memory cell. In short, the signal data stored in the memory cell matrix will be the exclusive OR relationship between the row address code and the column address code.
The process of FLASH parity graphics function detection is: first write the background graphics according to the algorithm, then read out bit by bit and check the correctness of the results, then erase the chip data, and repeat the above test process with the inverted graphics. The total number of test steps is M=4N.
Since the parity pattern is asymmetric, the failure of any one-bit address decoder will cause repeated addressing of one of the two memory cells that should have written inverse data to each other, and the second addressing changes the first address. The content written during the secondary addressing, while the other memory location is not accessed. Therefore, the address parity pattern can well detect the failure of the address decoder.
In addtion, the parity pattern writes the entire memory cell every time and then reads it out as a whole. There is no repeated erasing process (the whole process only needs to be erased twice), which is very suitable for FLASH chip testing.
2) Step-by-Step Method
The step-by-step method is a method in which each cell of the memory is checked in turn. First, starting from the first storage unit, each unit is inverted and checked one by one, and one scan is not completed until the end of the last unit detection. Then, in the case of reverse code, starting from the first storage unit, each unit is inverted and checked one by one, until the end of the last unit detection. The whole process is as if all the units are walking forward together, hence the name “step-by-step method”. According to the characteristics of the FLASH chip, we change the process of walking under the background of the reverse code, and transform it as follows to form a suitable synchronizing algorithm.
Before testing, each memory cell has information “1”. First, write the background pattern in the storage matrix (the initial state is all “1”), then start from address A0 to read “1”, write “0”, read “0”, and check the readout result. Then, repeat the operation (read “1”, write “0”, read “0”) to the next address selection unit in turn, until all storage units (A=N-1) are repeated. Then in the read operation mode, perform a forward scan and read out on all the memory cells to check whether there is a problem of multiple writing in the forward and reverse directions. The memory input is then erased so that all cells are all “1”s. Then start the reverse scan: starting from the highest address AN-1, read “1”, write “0”, read “0”, and perform the above operation process bit by bit until the final address is AN-1, and finally all memory cells having a read “0” scan is performed to verify the correctness of the readout.
Testing the memory chips with this test algorithm allows each memory cell to be accessed. It can not only ensure that each memory cell can store “1” and “0” data, but also ensure that each memory cell is subject to reading “1”, reading “0” and writing “1” and writing “0” from other surrounding cells of the interruption. The total number of test steps for this method is:
In formula (3), W represents a write operation, R represents a read operation, Q represents “1”, and represents “0”. Bij represents the memory cell in the i-th row and j column of the memory. For example, WBij(Q) represents the time taken to write a “1” operation to the memory cell of the i-th row and j column. It can be seen from formula (3) that the total number of test steps is 9N, and the whole process only needs two erasing operations, which shows that it is a fast and effective method.
3) Mobile Reverse Method
It is a method of inverting the data of each address storage unit in sequence. It needs to read the data of each storage unit before and after the inversion, and it must also generate address jumps by means of the forward and backward address addressing sequence, and the address changes in increments of 20, 21…, 2n-1 power ( n is the number of address bits). After the address jump is performed according to the above rules, three operations are performed on each address: read-write-read is a cycle.
The purpose of the above operation is mainly to generate effective mutual interference between addresses, but obviously, if the above operation is performed with the entire chip as a unit, data needs to be erased multiple times, so the FLASH test chip should be improved in this way: the operation is completed in units of sectors. Assuming that the FLASH chip has N sectors, the function test of the mobile inversion method must first write all memory cells with “1” as the background pattern. First, in the first sector, read and verify that the A0 storage unit is “1”, then rewrite the storage unit to “0”, and finally read the information of the storage unit to prove the newly written “0” still exists in this storage unit. The test address of the first sector is incremented by the order of 20 valid bits, and the above operation process of reading “1”, writing “0” and reading “0” must be repeated for each storage unit, and the test step size is 3n (n is the number of storage units in the sector) can make all storage units become “0”. The address sequence of this test is incremented by 1, that is, from the lowest address bit A0 to the highest bit A (n-1), read “1”, write “0” and read ” 0″ to verify.
For the second sector, the next address level 21 is used as the change amount of the address increment, and different address bits are used as the lowest bit each time (the 0th bit and the 1st bit respectively), so that the address changes by this increment. through all possible addresses. Therefore, in a test program, all memory cells of addresses are tested once. Then, take 22, 24…2N as the address increment in turn, repeat the above process, and generate a new cyclic carry every time a cycle is completed.
Because the size of each sector is different, the step size of the test pattern of the mobile reverse method is 3n (n is the maximum number of storage units in the sector). The sector-based test is actually a random test of the chip function, because it does not repeatedly disturb the access data of each unit to verify the influence of signal changes between its address lines, but this in the method, the adjacent address lines are tested one by one in each sector. Since the structure of each sector is basically the same, this sampling test is very representative, and the test time is reduced by an order of magnitude.
The method test pattern is a good compromise test scheme. Because it has almost the best characteristics of various test patterns, it can test the disturbance interaction between as many memory cells as possible with fewer test steps. In the specific procedure, the “1” field is reversed to the “0” field, which is generated by selecting addresses in sequence and writing these addresses, and there is a write operation between the two reads. The mobile inversion test includes functional test and dynamic test. The former test ensures that the memory cell under test is not affected by reading and writing other memory cells, while the latter test predicts the fetch time under the worst and best conditions, and predicts the impact to the address transition on these times.
This test method is easy to implement. It is based on the skipping algorithm and reduces the complexity of the algorithm by changing the length of the skipping step. The mobile inverse method test is a test pattern with good functional test and dynamic test characteristics, and it requires a short test time and has good results in many cases. This method is especially effective for testing larger-capacity memories.
The method can also be further expanded, that is, the data is processed by mobile inversion. Taking the chip as a 32-bit bus as an example, first write 0xAAAAAAAA to each unit of the memory, verify and erase, then write 0xCCCCCCCC to the memory, verify and erase, and then write 0xF0F0F0F0, 0x0F0F0F0F, 0xFF00FF00, 0x00FF00FF, 0xFFFF0000, 0x0000FFFF, 0xFFFFFFFF, and 0x0 in sequence, finally erase the data after verifying the correctness of the writing. The principle is the same as that of address movement inversion, which is not repeated here.
3.3 Comprehensive Use of Test Methods and Flow Test
In the above, the testability of the FLASH chip is improved from the point of view of the algorithm. Although the NOR and NAND FLASH structures are different, the above algorithms can be used to test the above two types of devices because the above algorithms can be calculated to generate test patterns in sequence.
The above three methods have their own advantages and can be used together in practical applications. The address parity pattern test is the most convenient and efficient, because only one address line is changed each time in the process of writing the pattern, and the opposite data is written, so if any address line is short-circuited, it will be checked immediately. This method is most suitable for checking the failure of the address decoder. The step-by-step method is suitable for checking the failure of multiple address selections and decoders, and can detect the influence of noise on the characteristics of memory chips during writing. It can ensure correct address decoding and the storage of “1” and “0” in each memory cell. In most production tests, the combination of these two methods can identify the vast majority of FLASH failures.
Of course, the chips produced by various manufacturers have certain differences in structure and process, so the probability of various errors is also different, and the method can be adjusted according to the actual situation. Due to design problems, some chips may have other less common errors, which require more detailed testing. In this case, it is more appropriate to use the mobile reverse test method. This method can well test the dynamic error of the chip, and can expand the test in detail or simplify the test according to specific needs, which is very effective for product performance analysis.
In the specific program design, in order to simplify the execution of the algorithm, the statement of reading the product model and calling the read and write commands can be stored in the tester as a subroutine, which can be seamlessly called every time it is needed.
In the testing process, the most time-consuming operation is the program erasing operation, which often takes several seconds at a time. The solution is to deal with the erasing process separately. In a practical application, two testers can be used, where several chips run in parallel while erasing. In this way, one device is used for reading, writing, and testing, and the other device is used for erasing data, which can effectively form a pipeline operation and greatly save test time. In addition, combining several methods can also help improve fault coverage.
3.4 Experimental Result
According to the above thought, on the test system platform of BC3192, both AMD's NOR-type FLASH Am29LV400B and Samsung's NAND-type FLASH 9F5608UOB have been tested. Experiments show that, compared with the traditional checkerboard-based test pattern, the parity method, the step-by-step method and the reverse method generate higher fault coverage of the test pattern. These algorithms have only two chip erase operations at most. Therefore, the test time can fully meet the needs of engineering testing. Among them, the mobile reverse method has no erase operation, so the test speed is the fastest. In the experiment, we use any one of the above three methods to test according to the method of running water. Under the same fault coverage, the test efficiency can be improved by more than 40%.
4 Conclusion
This paper is an attempt to test FLASH on the basis of traditional memory test theory. This method retains the advantages of traditional methods and better solves the difficulty of FLASH memory test. The method is convenient and quick, the process is simple, and all test patterns can be generated in advance, so that they can be directly loaded into the tester, which is beneficial to be directly applied to the tester for production testing.
